This invention relates to a method for fabricating a semiconductor memory device, and more particularly to a semiconductor memory device and a method for fabricating the same where a ferroelecric film is used as a dielectric film of a capacitor.
In general, a ferroelectric memory device is nonvolatile and the data stored in the ferroelectric memory device are not removed in power off. However, if the thickness of the dielectric capacitor is very thin, spontaneous polarization is fast occurred so that the ferroelectric memory device is able to read out the data therefrom or write the data therein with high speed. The ferroelectric memory device may constitute memory cells which each thereof is comprised of a transistor and a ferroelectric capacitor so that it is applicable to semiconductor memory device with large capacity. There are typically SrBi2Ta2O9(SBT), PZT and PbZrO3 as the ferroelectric film.
FIG. 1 is a diagram illustrating a method for fabricating a capacitor using SBT film as a dielectric film. Referring to FIG. 1, on a semiconductor substrate 11 where a node (not shown) is formed, a first intermediate insulating layer 12 is formed. A glue layer 13 and a conduction layer 14 for storage node are formed on the first intermediate insulating layer 12 in turn. A Ti layer is used for the glue layer 12 and a Pt layer is used for the conduction layer for storage node. A SBT film 15 is deposited on the conduction layer 14 and a conduction layer 16 for plate node is deposed on the SBT film.
The conduction layer 16 for plate node and the SBT film 15 are patterned. Then, a second intermediate insulating layer 17 is deposited over the conduction layer 14 for storage node including the SBT film 15 and the conduction layer 16 for plate. At this time, a spin on glass (SOG) film having a planarization property is used for the second intermediate insulating layer 17.
The second intermediate insulating layer 17 is etched to expose a selection portion of the conduction layer 16 for plate electrode. An A1 metal layer 18 is formed on the second intermediate insulating layer to be contacted with the exposed conduction layer 16 for plate node. An antireflection film 19 is formed on the Al metal layer 18 and the A1 metal layer 18 and the antireflection film 19 are patterned to form a metal interconnection layer 20.
However, if a high temperature process such as the second intermediate insulating layer formation process is accomplished following the SBT film deposition, bismuth(Bi) within the SBT film 15 is easily volatile so that the hysterisis property of the SBT film is degraded.
Furthermore, the SBT film 15 is apt to damage by the following process and in depositing the second intermediate insulating layer 17, the exposed portion of the SBT film 15 and chemicals for forming the second intermediate insulating layer 17 are reacted with each other so that leakage current flows through the SBT film 15. Therefore, reliability of the memory devices is degraded.